There are a variety of electrical interconnect techniques used for providing connections between electrical components. Interconnects vary widely in their use and function as do the variety of electrical components being connected. Electrical components can be interconnected by soldering, wire bonding, Tape Automated Bonding (TAB), or metal strips, for example. Plated ceramic interconnects also can be used for forming interconnects. These and other interconnect techniques can be used to interconnect a variety of integrated circuit (IC) components, and one example includes the techniques used for packaging of integrated circuit chips and surface mounting them on printed circuit boards (PCB's). The following background description relates to the prior art of forming electrical interconnects used in the packaging of integrated circuit chips and the mounting of IC packages on PCB's. This description is an example only, and is intended to simply provide a better appreciation of the improvements resulting from the present invention as applied to surface connection of electrical components in general. Other applications of the invention will be more fully understood when considering the various embodiments of the invention described in greater detail at a later point.
Perhaps the most widely used technique for packaging integrated circuit chips and mounting them on PCB's is that of encapsulating a chip in an epoxy or ceramic package. In this technique, the chip is first mounted at the center of a plurality of radially extending leads. Then, fine wires are soldered onto wire bonding pads on the chip. The opposite end of each of these wires is soldered to the inner end of one of the radial leads. This process for electrically connecting the chip to the leads with fine wires is called "wire bonding." The chip and the inner end of each radial lead are then encapsulated in epoxy or ceramic, with the outermost end of each lead being left exposed. The exposed ends of the leads are bent downward so that they may be plugged into an integrated circuit chip socket mounted on the printed circuit board. In this way, the chip is electrically and mechanically coupled to the printed circuit board. This method of mounting and packaging integrated circuits has disadvantages, which include the integrated circuit chips being occasionally damaged when wires are soldered to the wire bonding pads on the chip surface.
In one widely used technique for surface mounting IC packages to printed circuit boards, a metal leadframe is used to make electrical connections between an integrated circuit and a PCB. Metal leadframes are stamped or etched from a thin, flat strip of metal to form outwardly extending pin-like members or leads. Generally, the metal leadframe is embedded in a molded plastic body or is otherwise affixed in a ceramic or plastic body with the leads extending out from the sides between the top and bottom surfaces of the body. The leads are typically bent downward along the sides of the body to what is commonly referred to as a J-shape, or a wing shape, or straight down to what has been referred to as a butt end, for allowing the packages to be surface mounted on the PCB. Surface mounting is an arrangement in which the leads are soldered to the surface of the PCB, as opposed to an arrangement in which the leads extend through plated thru-holes in the PCB before soldering.
In one prior art IC package having J-shaped leads, the body has a castellated edge which extends downwardly around the bottom side of the body. Separate leads are bent in an S-shape around the raised castellations. This provides a spacing between the bottom of the IC package and the PCB. U.S. Pat. No. 4,012,766 to Phillips, et al. discloses a semiconductor package and a method of manufacturing of the general type which includes J-shaped leads.
Use of a leadframe has disadvantages. For example, as input/outputs (I/O's) have increased in number, the spacing between leads has decreased so as to prevent the IC packages from becoming excessively large. As a result, the leadframes have been forced to become thinner. For these reasons, normal testing, shipping and handling procedures have become very difficult because of the need to avoid bending the external leads. Any bending of the metal leads can cause a lateral misalignment which can prevent the bent leads from matching up with corresponding contacts on a PCB. Bending of the leads can also cause a non-planar misalignment of the leads at the bottom of the IC package, and, as a result, some of the leads may not be connected to a corresponding contact on the PCB.
Another arrangement for surface mounting of IC packages comprises a printed wiring board in the form of a thin plastic base on which metalized leads are formed in a pattern. The metalized leads are typically formed by laminating copper to the board with an epoxy resin and etching away to form the metalized leads. Holes are drilled in "picture frame" arrays through the thin dimension of the base, from the top to the bottom, and, subsequently, the holes are plated with metal such as copper or gold. The printed metal leads on the top side of the base are then plated with gold or the like to form a pattern of printed leads which fan out from a rectangular central portion of the carrier to the plated thru-holes. Small metalized leads are also formed on the bottom side of the base below the plated thru-holes. An IC chip is then mounted within a cavity in the central portion of the base, and fine conductive wires are bonded between the chip and the ends of the metal leads. The top of the base is then covered with a plastic lid, or potted with epoxy resin. The resulting assembly is placed on a PC board, with the bottom side of the base resting against the top face of the board. Flow soldering techniques are used to form electrical connections between each etched metal lead on the bottom side of the base and a corresponding contact on the PCB.
The plastic IC package with the etched metal traces is useful because there are no self-supporting metal wires or leads which can be bent, inasmuch as the etched metal leads are affixed firmly to the surface of the base and, therefore, do not move. However, this approach has disadvantages because the etched metal leads on the bottom of the base can result in electrical shorts from trace to trace on closely spaced traces when soldering the base to a PCB. This, therefore, limits the pitch of the metal traces of the package, i.e., its capability of being expanded into providing much finer pitches and resulting higher I/O's. The use of printed wiring board techniques, including use of the thick conductive metal leads, also limits the board's applicability to finer lead pitches.
Ceramic leadless IC packages have also been used in the past for mounting integrated circuits to a PCB. One prior art ceramic leadless IC package is disclosed in U.S. Pat. No. 4,525,597 to Abe, in which circuit patterns are printed on a ceramic green sheet with a metalizing paste. An insulating layer is then placed over the metalized pattern on the top surface. The green sheet is then hot pressed to make the top surface concave and the bottom surface convex around a peripheral rim of the ceramic body. The green sheet is then fired. After firing, the ceramic is plated with a conductive metal at positions corresponding to the exposed metal circuit patterns remaining on the ceramic. The step of hot pressing the ceramic body forms a series of spaced apart depressions around the periphery in the top surface, with corresponding stand-off pads on the bottom surface of the ceramic body.
This ceramic IC carrier has several disadvantages. It is limited in its ability to provide fine lead pitches, because the steps involved in forming a ceramic carrier by casting in green sheets, applying a metal paste, hot pressing, firing, and subsequent metal plating techniques limit resolution. These techniques therefore are not adaptable to producing an IC carrier with the geometries necessary to produce a fine lead pitch. In addition, surface mounted ceramic IC packages can be unreliable because thermal transients can develop shear forces at the solder joints and produce fatigue and resulting poor electrical connections. As lead pitches become finer, these problems with ceramic IC packages become magnified. The more reliable ceramic IC packages to date have the self-supporting metal leads which have the disadvantages of the leadframe approach described above.
Thus, the prior art has provided a variety of electronic interconnect techniques for a wide variety of electrical components, including the previously described techniques for surface mounting of IC packages. All of these interconnect techniques have disadvantages or limitations which are overcome by the present invention.